English Introduction
	Chinese Introduction

 

Introduction to Laboratory for Reliable Computing

The Laboratory for Reliable Computing at the EE Department of National Tsing Hua University (NTHU) includes ten faculty members (Professors Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang, Hsi-Pin Ma, Jenn-Chyou Bor, Jing-Jia Liou, Po-Chiun Huang, Shi-Yu Huang, Tsin-Yuan Chang and Cheng-Wen Wu) and more than one hundred and sixty graduate (MS and PhD) students. Professors Chang and Wu in the past few years have been offering to the EE graduate students courses on VLSI Design, VLSI Algorithms, Computer Arithmetic, Computer Architecture, VLSI Testing, and Fault Tolerant Computing. Their lab has received multi-million-dollar (in NT dollars) research contracts and grants from both the government and the industry each year. Together with four other young and energetic faculty members from the CS Department whose expertise covers a wide range of topics in computer-aided VLSI design, the NTHU group is showing a rapid growing strength in theoretical and practical research. Their research activities are focused in the areas of testable and fault tolerant VLSI circuit/system design and test. I n testable VLSI systems design, stress has been placed on the study of testing and testable design techniques for high performance application specific VLSI systems, especially those with a regular structure. With the rapid progress of VLSI technology and the increasing quest of high speed digital signal processing hardware, iterative logic arrays (ILAs) are becoming more and more popular due to their superiority in computational performance and ease of design and test. The NTHU team's study of ILAs stands out and has provided theory and techniques for C-testable and M-testable ILA design, and test generation of various ILAs, including unilateral and bilateral arrays, combinational and sequential arrays, hexagonally connected and octagonally connected arrays, multidimensional arrays, and arrays with sequential faults. This study has led the way to important results on easily testable design of high speed cellular-array multipliers, differential-cascode-voltage-switch (DCVS) finite-field multipliers, and high performance digital-signal-processing (DSP) and communications circuits. I n fault tolerant VLSI systems design, concurrent error detection theory and techniques have been emphasized, which include design of conventional (i.e., gate-level circuits modeled by single stuck-at faults and/or unidirectional faults) and CMOS self-checking checkers (modeled by switch-level faults, in addition to classical faults), Iddq design-for-testability schemes (using on-chip current sensor circuits), and concurrent error detectable FPLAs, arithmetic circuits (e.g., multipliers), and interconnection networks (e.g., FFT butterfly networks). They are also interested in fault tolerant memory system architectures, and have reported results on highly reliable fault tolerant interleaved memory systems for uniprocessor and multiprocessor computer architectures.

LaRC簡介

近 幾年來超大型積體電路的製造技術進步神速，其複雜度已使設計的方法 必須大量的依賴電腦及自動化的程式幫忙，因而 VLSI/CAD 已成為重要 的研究領域之一。目前本實驗室由十位老師(吳誠文老師、張慶元老師 、黃錫瑜老師、黃柏鈞老師、劉靖家老師、柏振球老師、馬席彬老師、張孟凡老師、鄭桂忠老師及謝志成老師) 共同指導，計有碩博士生160多位，皆專精於 VLSI 設計、驗證及測試 、計算機算術、演算法和架構、數位類比混合式通訊 VLSI 以及CMOS RF 設計之相關研究。每年亦積極與國科會和工業界進行產學合作計畫 ，協助開發、提升產業技術水準，維繫良好互動關係。 目 前本實驗室的設備已有 SUN 工作站及 Pentium PC 數十部，各式數位 / 類比量測儀器包含示波器、邏輯分析儀及信號源產生器等以協助實 體晶片和系統的實作與量測。同時在國科會晶片中心的支援下，各式 設計軟體均與工業界同步。完善的軟硬體設備，配合厚實的研究團隊 ，足以應付各種複雜的設計與挑戰，培植優秀的設計人才。